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Bit
Name
Description
At the start of a DMA cycle, or 2 DMA transfer, the controller fetches the channel_cfg from system
memory. After it performs 2 , or N, transfers it stores the updated channel_cfg in system memory.
When the controller operates in peripheral scatter-gather mode, you must only use this
value in the alternate data structure.
R
R
The controller does not support a dst_size value that is different to the src_size value. If it detects a
mismatch in these values, it uses the src_size value for source and destination and when it next updates
the n_minus_1 field, it also sets the dst_size field to the same as the src_size field.
After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the
channel_cfg data is invalid. This prevents it from repeating the same DMA transfer.
8.4.3.4 Address calculation
To calculate the source address of a DMA transfer, the controller performs a left shift operation on the
n_minus_1 value by a shift amount that src_inc specifies, and then subtracts the resulting value from the
source data end pointer. Similarly, to calculate the destination address of a DMA transfer, it performs a
left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and then subtracts
the resulting value from the destination end pointer.
Depending on the value of src_inc and dst_inc, the source address and destination address can be
calculated using the equations:
src_inc = b00 and dst_inc = b00
src_inc = b01 and dst_inc = b01
src_inc = b10 and dst_inc = b10
src_inc = b11 and dst_inc = b11
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?
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source address = src_data_end_ptr - n_minus_1
destination address = dst_data_end_ptr - n_minus_1.
source address = src_data_end_ptr - (n_minus_1 << 1)
destination address = dst_data_end_ptr - (n_minus_1 << 1).
source address = src_data_end_ptr - (n_minus_1 << 2)
destination address = dst_data_end_ptr - (n_minus_1 << 2).
source address = src_data_end_ptr
destination address = dst_data_end_ptr.
Table 8.10 (p. 56) lists the destination addresses for a DMA cycle of six words.
Table 8.10. DMA cycle of six words using a word increment
Initial values of channel_cfg, prior to the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = b101, cycle_ctrl = 1
End Pointer
0x2AC
0x2AC
Count
5
4
Difference
0x14
0x10
1
Address
0x298
0x29C
DMA transfers
0x2AC
0x2AC
0x2AC
0x2AC
3
2
1
0
0xC
0x8
0x4
0x0
0x2A0
0x2A4
0x2A8
0x2AC
This value is the result of count being shifted left by the value of dst_inc.
Final values of channel_cfg, after the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = 0, cycle_ctrl = 0
1
Table 8.11 (p. 57) lists the destination addresses for a DMA transfer of 12 bytes using a halfword
increment.
2011-04-12 - d0001_Rev1.10
56
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